Synchronous memory devices can operate with data access latencies. A write latency can be the number of clock cycles between the application of a write instruction (and/or address) and the application of write data at data inputs.
Synchronous memory devices can also include a “late” write option. A late write option can defer the writing of data into a memory cell array for a number of clock cycles. Conventional late write options typically defer writes for small number of cycles (i.e., 2-3 cycles). Corresponding to a late write option can be data forwarding. In a data forwarding operation, a read operation can be directed to write data that has yet to be written into a memory cell array. Such write data can be forwarded as read data.